1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device on which a large-scale memory circuit is mounted.
2. Description of the Prior Art
With recent improvements in the semiconductor machining technology, it has become possible to mount a large-scale memory cell unit on semiconductor integrated circuit devices. In general, large-scale memory cell units have a larger packaging density than logic circuits, and therefore can be easily failed components. Conventionally, repair techniques of preparing redundant areas, and making each of the redundant areas take the place of a defective word or bit in a memory cell, which is found by a post-manufacturing test, have been used as a method of repairing defective parts of a memory cell unit during manufacturing. Repair techniques include a fuse-type memory repair technique of physically opening the circuit formed by a fuse corresponding to a defective part to disconnect the defective part from a memory cell unit using laser light, and substituting a redundant unit for the defective part. Japanese patent application publication (TOKKAIHEI) No. 4-372798 discloses such a repair method of repairing defective parts in a memory cell unit located in a prior art semiconductor integrated circuit device.
A problem with a prior art semiconductor integrated circuit device constructed as above is that the use of a fuse-type memory repair technique of physically opening the circuit formed by a fuse corresponding to a defective part to disconnect a defective part from a memory cell unit disposed in a large-scale memory increases the manufacturing cost because of a physical post-manufacturing wiring and testing of the large-scale memory.